/Score-based Dual Bank Refresh Arbitration
Abstract

An apparatus and method for adaptive memory refresh scheduling utilize a score-and-filter-based arbitration logic to select bank pairs for refresh operations. A score generation logic determines priority scores for memory banks based on current operational states, including bank page states and transaction histories. A multi-stage filtering process identifies eligible banks by evaluating timing constraints and bank-refresh window requirements. A dual-stage arbitration logic processes the priority scores of the eligible banks to identify an optimal bank index and bank group pair. The arbitration logic employs parallel arbiters and weighted summation logic to select a winning bank index for generating a dual-bank refresh command. By dynamically selecting refresh candidates based on real-time bank activity and state transitions, the system manages refresh scheduling to maintain high throughput and bank utilization across varying workload conditions. The disclosed technology is applicable to high-performance memory controllers, including those compliant with dual-bank refresh protocols.

Full Text

What is claimed is:

An apparatus and method for adaptive memory refresh scheduling utilize a score-and-filter-based arbitration logic to select bank pairs for refresh operations. A score generation logic determines priority scores for memory banks based on current operational states, including bank page states and transaction histories. A multi-stage filtering process identifies eligible banks by evaluating timing constraints and bank-refresh window requirements. A dual-stage arbitration logic processes the priority scores of the eligible banks to identify an optimal bank index and bank group pair. The arbitration logic employs parallel arbiters and weighted summation logic to select a winning bank index for generating a dual-bank refresh command. By dynamically selecting refresh candidates based on real-time bank activity and state transitions, the system manages refresh scheduling to maintain high throughput and bank utilization across varying workload conditions. The disclosed technology is applicable to high-performance memory controllers, including those compliant with dual-bank refresh protocols.
Timeline
Filed
04/01/2026
Published
08/06/2026
Granted
Not Available
IPC Codes(1)
G06F 3/06:Digital input from, or digital output to, record carriers