/Method To Produce A 3d Multilayer Semiconductor Device And Structure
Abstract

Methods of making a 3D multilayer semiconductor device including: providing a first level with a first single crystal silicon layer (1stSCSL) and a second level including a 2ndSCSL; performing epitaxial growth of a first SiGe-layer on top of the 2ndSCSL; performing epitaxial growth of a 3rdSCSL on top of the first SiGe-layer, where the 3rdSCSL has an average thickness of less than 2,000 nm; forming first transistors each including a single crystal channel, where the forming of first transistors includes performing an epitaxial growth of a second SiGe-layer on top of the 3rdSCSL; forming metal layers interconnecting the first transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL, where at least one of the first transistors include at least one gate-all-around channel.

Full Text

What is claimed is:

Methods of making a 3D multilayer semiconductor device including: providing a first level with a first single crystal silicon layer (1stSCSL) and a second level including a 2ndSCSL; performing epitaxial growth of a first SiGe-layer on top of the 2ndSCSL; performing epitaxial growth of a 3rdSCSL on top of the first SiGe-layer, where the 3rdSCSL has an average thickness of less than 2,000 nm; forming first transistors each including a single crystal channel, where the forming of first transistors includes performing an epitaxial growth of a second SiGe-layer on top of the 3rdSCSL; forming metal layers interconnecting the first transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL, where at least one of the first transistors include at least one gate-all-around channel.
Timeline
Filed
04/11/2026
Published
08/13/2026
Granted
Not Available
IPC Codes(1)
H10D 88/00:Three-dimensional [3D] integrated devices