/Memory System, Method Of Operating Memory System, And Computer-readable Storage Medium
Abstract

According to one aspect of the present disclosure, a memory system is provided. The memory system may include at least one memory. The at least one memory may include a memory array coupled to n wordlines. The n wordlines may be sequentially arranged by physical wordline identifiers, where n≥2. The memory system may include a memory controller coupled to the at least one memory. The memory controller may obtain multiple pieces of data to be written into the memory array. The memory controller may map n physical wordline identifiers to n virtual wordline identifiers. The physical wordline identifiers may respectively correspond to m adjacent virtual wordline identifiers spaced apart from each other, where 2≤m ≤n. The memory controller may generate check data based on data corresponding to the m adjacent virtual wordline identifiers. The check data may check and recover the data corresponding to the m adjacent virtual wordline identifiers.

Full Text

What is claimed is:

According to one aspect of the present disclosure, a memory system is provided. The memory system may include at least one memory. The at least one memory may include a memory array coupled to n wordlines. The n wordlines may be sequentially arranged by physical wordline identifiers, where n≥2. The memory system may include a memory controller coupled to the at least one memory. The memory controller may obtain multiple pieces of data to be written into the memory array. The memory controller may map n physical wordline identifiers to n virtual wordline identifiers. The physical wordline identifiers may respectively correspond to m adjacent virtual wordline identifiers spaced apart from each other, where 2≤m ≤n. The memory controller may generate check data based on data corresponding to the m adjacent virtual wordline identifiers. The check data may check and recover the data corresponding to the m adjacent virtual wordline identifiers.
Timeline
Filed
04/14/2026
Published
08/20/2026
Granted
Not Available
IPC Codes(3)
G11C 29/02:Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 8/08:Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 29/52:Protection of memory contents; Detection of errors in memory contents