Abstract
The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a conductive bottom plate is disposed over a semiconductor substrate. A conductive top plate is disposed over and spaced apart from the bottom plate by a first distance from a top surface of the bottom plate to a bottom surface of the top plate, the first distance being at least 15 μm. A polymer layer is disposed over the top plate, a second distance being from a top surface of the top plate to a bottom surface of the polymer layer, the second distance being at least 30% of the first distance.
Full Text
What is claimed is:
The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a conductive bottom plate is disposed over a semiconductor substrate. A conductive top plate is disposed over and spaced apart from the bottom plate by a first distance from a top surface of the bottom plate to a bottom surface of the top plate, the first distance being at least 15 μm. A polymer layer is disposed over the top plate, a second distance being from a top surface of the top plate to a bottom surface of the polymer layer, the second distance being at least 30% of the first distance.
Timeline
Filed
04/14/2026Published
08/20/2026Granted
Not AvailableIPC Codes(8)
H10W 20/40:Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
H10W 20/00:Interconnections in chips, wafers or substrates
H10W 20/41:characterised by their conductive parts