/Vertical Field Effect Transistor Device And Method Of Fabrication
Abstract

A vertical gallium nitride (GaN) field effect transistor (FET) device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed region and is substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and the recessed region is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed region. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate.

Full Text

What is claimed is:

A vertical gallium nitride (GaN) field effect transistor (FET) device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed region and is substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and the recessed region is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed region. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate.
Timeline
Filed
04/29/2026
Published
08/20/2026
Granted
Not Available
IPC Codes(4)
H10D 30/66:Vertical DMOS [VDMOS] FETs
H10D 30/01:Manufacture or treatment
H10D 62/17:Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions