/Managing Program Disturb In Memory Devices
Abstract

Example apparatus and methods are disclosed. In one example, a memory device can include a memory array and a peripheral circuit. The memory array including a first memory string comprising a first select gate transistor and memory cells stacked vertically. The peripheral circuit coupled to the first select gate transistor via a select line and to the memory cells via word lines. The peripheral circuit is configured to apply a program voltage to a first word line and apply a first voltage to the select line during a time period of a first program operation, and apply a program voltage to a second word line and apply a second voltage to the select line during a time period of a second program operation. The second word line is farther from the select line than the first line and the second voltage is higher than the first voltage.

Full Text

What is claimed is:

Example apparatus and methods are disclosed. In one example, a memory device can include a memory array and a peripheral circuit. The memory array including a first memory string comprising a first select gate transistor and memory cells stacked vertically. The peripheral circuit coupled to the first select gate transistor via a select line and to the memory cells via word lines. The peripheral circuit is configured to apply a program voltage to a first word line and apply a first voltage to the select line during a time period of a first program operation, and apply a program voltage to a second word line and apply a second voltage to the select line during a time period of a second program operation. The second word line is farther from the select line than the first line and the second voltage is higher than the first voltage.
Timeline
Filed
04/14/2026
Published
08/20/2026
Granted
Not Available
IPC Codes(5)
G11C 16/10:Programming or data input circuits
G11C 16/04:using variable threshold transistors, e.g. FAMOS
G11C 16/08:Address circuits; Decoders; Word-line control circuits