A semiconductor IC chip comprising: a silicon substrate; a first transistor at a top surface of the silicon substrate; a first through silicon via (TSV) vertically in the silicon substrate; a second through silicon via (TSV) vertically in the silicon substrate; a first interconnection scheme on the top surface of the silicon substrate, wherein the first interconnection scheme comprises an insulating dielectric layer, a metal via in the insulating dielectric layer, a metal pad on a bottom surface of the insulating dielectric layer and a bottom surface of the metal via and coupling to the first TSV, and a first metal interconnect coupling the second TSV to the first transistor; and a second interconnection scheme on a bottom surface of the silicon substrate, wherein the second interconnection scheme comprises a second metal interconnect coupling the first TSV to the second TSV; and a first metal contact at a top of the semiconductor IC chip and on a top surface of the first interconnection scheme, wherein the first metal contact couples to the first transistor through, in sequence, the metal via, metal pad, first TSV, second metal interconnect, second TSV and first metal interconnect, wherein the first metal contact is configured for coupling to a voltage of power supply.