A memory device including a set of memory cells connected to a target wordline; and control logic, operatively coupled with the set of memory cells, to perform operations including: causing, during a programming time period, each pillar of a set of pillars associated with the target wordline to be boosted to a different voltage, wherein each pillar corresponds to a respective programming level of a set of programming levels associated with the target wordline; causing, during the programming time period, a programming pulse to be applied to the target wordline, wherein the programming pulse programs each programming level of the set of programming levels associated with the target wordline; and causing, during a program verify time period, a program verify voltage to be applied to the target wordline, wherein the program verify voltage is adjusted by a program verify (PV) voltage offset associated with an adjacent wordline of the target wordline.