/Memory Cell With A Buffer Layer And Its Fabrication Process
Abstract

Some embodiments relate to an integrated chip including a bottom electrode over a semiconductor substrate. A seed layer overlies the bottom electrode. A data storage structure is arranged on the seed layer. A first buffer layer is arranged between the bottom electrode and the seed layer. The first buffer layer is in physical contact with the seed layer and opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer.

Full Text

What is claimed is:

Some embodiments relate to an integrated chip including a bottom electrode over a semiconductor substrate. A seed layer overlies the bottom electrode. A data storage structure is arranged on the seed layer. A first buffer layer is arranged between the bottom electrode and the seed layer. The first buffer layer is in physical contact with the seed layer and opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer.
Timeline
Filed
04/20/2026
Published
08/27/2026
Granted
Not Available
IPC Codes(5)
H10B 61/00:Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
H10N 50/01:Manufacture or treatment
H10N 50/10:Magnetoresistive devices