/Power Semiconductor Apparatus And Bonding Method Thereof
Abstract

A method includes providing a device wafer including a semiconductor substrate and a metal layer disposed over the semiconductor substrate; patterning the metal layer to form a plurality of openings extending through the metal layer; forming a first adhesive layer over the metal layer, wherein the first adhesive layer is in direct contact with the semiconductor substrate through the plurality of openings; providing a backside support wafer; bonding the device wafer to the backside support wafer through the first adhesive layer; curing the first adhesive layer to secure the backside support wafer to the device wafer; and forming recessed regions in the semiconductor substrate corresponding to saw dicing lanes of the device wafer.

Full Text

What is claimed is:

A method includes providing a device wafer including a semiconductor substrate and a metal layer disposed over the semiconductor substrate; patterning the metal layer to form a plurality of openings extending through the metal layer; forming a first adhesive layer over the metal layer, wherein the first adhesive layer is in direct contact with the semiconductor substrate through the plurality of openings; providing a backside support wafer; bonding the device wafer to the backside support wafer through the first adhesive layer; curing the first adhesive layer to secure the backside support wafer to the device wafer; and forming recessed regions in the semiconductor substrate corresponding to saw dicing lanes of the device wafer.
Timeline
Filed
04/27/2026
Published
08/27/2026
Granted
Not Available
IPC Codes(6)
H10P 58/00:Singulating wafers or substrates into multiple chips, i.e. dicing
H10P 50/24:of semiconductor materials
H10P 54/40:by sawing, e.g. using revolving or reciprocating blades