A receiving circuit includes: a clock generating circuit configured to generate a reception clock signal; and a plurality of data receiving circuits configured to receive respective data signals based on the reception clock signal. The clock generating circuit includes: a clock receiving circuit configured to receive a reference clock signal; a variable delay circuit configured to generate a delayed reference clock signal by delaying the reference clock signal received by the clock receiving circuit by a delay amount responsive to a delay control signal; a polyphase shifter circuit including a filter circuit and configured to generate a plurality of internal clock signals by delaying the delayed reference clock signal successively; and a selector circuit configured to select one of the plurality of internal clock signals based on a phase selection signal and output the selected internal clock signal as the reception clock signal.