Abstract
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
Full Text
What is claimed is:
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
Timeline
Filed
04/27/2026Published
09/03/2026Granted
Not AvailableIPC Codes(4)
G06F 12/1009:using page tables, e.g. page table structures
G06F 12/0864:using pseudo-associative means, e.g. set-associative or hashing
G06F 12/1027:using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]