/Semiconductor Devices Having Gate And Source/drain Patterns
Abstract

A semiconductor device, includes, a first active pattern includes a first lower portion and a first channel layer spaced apart from the first lower portion, a second active pattern includes a second lower portion and a second channel layer spaced apart from the second lower portion, a channel semiconductor layer on the first lower portion and the first channel layer, a first gate pattern on the channel semiconductor layer, a second gate pattern on the second lower portion and the second channel layer, a first source/drain pattern connected to the first lower portion, the first channel layer, the channel semiconductor layer, and the first gate pattern, and a second source/drain pattern connected to the second lower portion, the second channel layer, and the second gate pattern, a lattice constant of the channel semiconductor layer being greater than a lattice constant of each of the first and second active patterns.

Full Text

What is claimed is:

A semiconductor device, includes, a first active pattern includes a first lower portion and a first channel layer spaced apart from the first lower portion, a second active pattern includes a second lower portion and a second channel layer spaced apart from the second lower portion, a channel semiconductor layer on the first lower portion and the first channel layer, a first gate pattern on the channel semiconductor layer, a second gate pattern on the second lower portion and the second channel layer, a first source/drain pattern connected to the first lower portion, the first channel layer, the channel semiconductor layer, and the first gate pattern, and a second source/drain pattern connected to the second lower portion, the second channel layer, and the second gate pattern, a lattice constant of the channel semiconductor layer being greater than a lattice constant of each of the first and second active patterns.
Timeline
Filed
05/01/2026
Published
09/03/2026
Granted
Not Available
IPC Codes(1)
H10B 12/00:Dynamic random access memory [DRAM] devices