Abstract
A decoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: decodes a plurality of sets of neural network information each of which identifies a neural network filter; decodes, from one access unit, two or more sets of activation information each of which specifies one set of neural network information among the plurality of sets of neural network information; and applies, to one picture, two or more neural network filters identified by two or more sets of neural network information specified by the two or more sets of activation information.
Full Text
What is claimed is:
A decoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: decodes a plurality of sets of neural network information each of which identifies a neural network filter; decodes, from one access unit, two or more sets of activation information each of which specifies one set of neural network information among the plurality of sets of neural network information; and applies, to one picture, two or more neural network filters identified by two or more sets of neural network information specified by the two or more sets of activation information.
Timeline
Filed
04/27/2026Published
09/03/2026Granted
Not AvailableIPC Codes(4)
H04N 19/42:characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (takes precedence H04N 19/635)
H04N 19/117:Filters, e.g. for pre-processing or post-processing (sub-band filter banks H04N 19/635)
H04N 19/136:Incoming video signal characteristics or properties