A memory controller that includes a buffer memory configured to store user data and a write command corresponding to a write request received from a host, a processor configured to control a memory device to perform a write operation, and a host interface configured to determine an active range based on mapping information of the memory device, determine the throttle trigger value based on the active range, determine a base latency based on a write ratio of the write command to commands received from the host, and determine a delay time of a write completion response based on the throttle trigger value and the base latency, delay the write completion response according to the delay time, and transmit the delayed write completion response to the host.