Abstract
In one example of the present technology, a method includes sending, by a CPU core of a processor, a direct memory access (DMA) stream setup command to an input/output (I/O) device, the DMA stream setup command comprising a virtual address; and sending, from the CPU core of the processor, a prefetch message comprising the virtual address to an input/output memory management unit (IOMMU) to cause the IOMMU to: prefetch a translation of the virtual address into a corresponding physical address from a main memory; and store the translation of the virtual address into the corresponding physical address in a translation lookaside buffer (TLB) of the IOMMU.
Full Text
What is claimed is:
In one example of the present technology, a method includes sending, by a CPU core of a processor, a direct memory access (DMA) stream setup command to an input/output (I/O) device, the DMA stream setup command comprising a virtual address; and sending, from the CPU core of the processor, a prefetch message comprising the virtual address to an input/output memory management unit (IOMMU) to cause the IOMMU to: prefetch a translation of the virtual address into a corresponding physical address from a main memory; and store the translation of the virtual address into the corresponding physical address in a translation lookaside buffer (TLB) of the IOMMU.
Timeline
Filed
05/04/2026Published
09/10/2026Granted
Not AvailableIPC Codes(4)
G06F 12/1045:associated with a data cache
G06F 12/02:Addressing or allocation; Relocation (program address sequencing G06F 9/00; arrangements for selecting an address in a digital store G11C 8/00)
G06F 12/06:Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication (takes precedence G06F 12/08)