A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.