/Semiconductor Device, Method For Fabricating The Semiconductor Device, And Memory Device And System Including The Semiconductor Device
Abstract

A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.

Full Text

What is claimed is:

A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.
Timeline
Filed
05/04/2026
Published
09/10/2026
Granted
Not Available
IPC Codes(4)
H10W 20/20:Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
G11C 16/04:using variable threshold transistors, e.g. FAMOS
H10B 43/27:the channels comprising vertical portions, e.g. U-shaped channels