A circuit for generating adaptive SET pulse currents for phase-change memory (PCM) cells. The circuit includes a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current with a programmable profile, the programmable profile comprising a constant current phase at a predefined set current, a first ramping-down phase from the predefined set current to a minimum cutoff current, a second ramping-down phase from the minimum cutoff current to zero, and a zero-current phase, wherein the constant current phase for each IDAC starts in response to the other IDAC starting the second ramping-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate the adaptive SET pulse currents.