A device includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each of which receives a data input signal and generates a first data output signal. Each receiver includes a delay line that is devoid of a duty cycle corrector (DCC), that has a predetermined number of delay elements, and that introduces a propagation delay to the data input signal by a fixed amount that substantially matches a propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to a data signal-receiving device.