Abstract
A delay-enhanced inverter circuit (DE-inverter) includes: a first non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node; and a capacitive device feedback-coupled between the first node and the second node, the capacitive device including: a first positive-channel metal-oxide (PMOS) field-effect transistor (FET) (PFET) feedback-coupled between the first node and the second node, the first PFET having a capacitor-configuration; and a first negative-channel metal-oxide (NMOS) FET (NFET) feedback-coupled between the first node and the second node, the first NFET having a capacitor-configuration.
Full Text
What is claimed is:
A delay-enhanced inverter circuit (DE-inverter) includes: a first non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node; and a capacitive device feedback-coupled between the first node and the second node, the capacitive device including: a first positive-channel metal-oxide (PMOS) field-effect transistor (FET) (PFET) feedback-coupled between the first node and the second node, the first PFET having a capacitor-configuration; and a first negative-channel metal-oxide (NMOS) FET (NFET) feedback-coupled between the first node and the second node, the first NFET having a capacitor-configuration.
Timeline
Filed
05/21/2026Published
09/17/2026Granted
Not AvailableIPC Codes(3)
H03K 19/0185:using field-effect transistors only
H03K 19/00:Logic circuits, i.e. having at least two inputs acting on one output (circuits for computer systems using fuzzy logic G06N 7/02); Inverting circuits
H03K 19/0948:using CMOS