A method of forming a memory cell includes forming a first active region providing first nano-structures for a write-port pass-gate transistor, forming a second active region providing second nano-structures for a write-port pull-up transistor, and forming a third active region providing third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region has a third width. The third width is larger than the first width, and the first width is larger than the second width.