A gate driving circuit includes a plurality of first odd main stages configured to drive first odd gate lines of a first display block in a first display period, a plurality of second odd main stages configured to drive second odd gate lines of a second display block adjacent to the first display block in a second display period, an odd reset dummy stage configured to reset a Q node included in a first lower-priority operation stage that is relatively late in operation order among the plurality of first odd main stages in the first display period; and an odd set dummy stage configured to set a Q node included in a first higher-priority operation stage that is relatively advanced in operation order among the plurality of second odd main stages in the second display period.