A method for forming a semiconductor device structure includes depositing a sacrificial gate structure over first and second fin structures formed from a substrate, each comprising alternatingly stacked first and second semiconductor layers; forming a source/drain feature between the fin structures, the source/drain feature comprising a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer surrounded by the second epitaxial layer, the third epitaxial layer having a first dopant concentration; forming a source/drain cap layer on the second and third epitaxial layers, the source/drain cap layer having a first thickness and a second dopant concentration greater than the first dopant concentration; removing the second semiconductor layers to expose the first semiconductor layers; forming a gate electrode layer surrounding the exposed first semiconductor layers; forming a silicide layer by depositing a metal source layer on the source/drain cap layer and performing a thermal anneal process, reducing the source/drain cap layer from the first thickness to a second thickness; and forming a metal capping layer on the silicide layer.