A method, system, and computer readable storage medium for operating an array of reconfigurable processing units with compiler-inserted quiesce boundaries. A compiler transforms a control flow graph of data processing operation into a transformed control flow graph by inserting into control flow graph additional vertices configured to sample whether a quiesce control signal has been received and to cause execution to wait at quiesce boundaries when the quiesce control signal has been received. Configuration data generated from the transformed control flow graph is loaded into the array to configure the array into execution fragment resource groups (EFRGs) that execute respective execution fragments. During execution the quiesce control signal is distributed to the EFRGs. In response to the additional vertices sampling that quiesce control signal has been received, execution waits at quiesce boundaries. The compiler may insert additional vertices in response to compiler directives, command-line options, or a configuration file.