Abstract
A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.
Full Text
What is claimed is:
A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.
Timeline
Filed
05/20/2026Published
09/17/2026Granted
Not AvailableIPC Codes(1)
G01R 31/317:Testing of digital circuits