A semiconductor device includes a substrate comprising a one time programmable (OTP) device region and a second region, a shallow trench isolation (STI) in the substrate disposed in both the OTP device region and the second region, and a first gate structure on the STI in the OTP device region. A top surface of the STI in the OTP device region is lower than a top surface of the STI in the second region. This cross-region height difference enables integration of OTP, I/O, and core devices on a single substrate and facilitates formation of dual step-shape profiles under the gate structure on the OTP device region for an enhanced and more concentrated electrical field.