/Cell Boundary Region With Buried Power Grid Segment, Semiconductor Device Including Same, And Method Of Manufacturing Same
Abstract

A method of forming a semiconductor device includes forming first and second active regions (ARs) in a substrate, forming pairs of gate segments, forming metal-to-source/drain region (MD) contact structures correspondingly over the first and second ARs and interspersed with pairs of gate segments, and forming a PG segment in a first buried metallization (BM_1st) layer (PGBM_1st segment) below the MD contact structures and on a back-side of the substrate. The first and second ARs having long axes extending in a first direction and being included correspondingly in first and second cell regions that abut relative to a second direction. Each pair including collinear first and second gate segments correspondingly over the first and second ARs, the first and second gate segments being spaced apart in the second direction. The PGBM_1st segment being electrically coupled to the at least one gap-spanning MD contact structure.

Full Text

What is claimed is:

A method of forming a semiconductor device includes forming first and second active regions (ARs) in a substrate, forming pairs of gate segments, forming metal-to-source/drain region (MD) contact structures correspondingly over the first and second ARs and interspersed with pairs of gate segments, and forming a PG segment in a first buried metallization (BM_1st) layer (PGBM_1st segment) below the MD contact structures and on a back-side of the substrate. The first and second ARs having long axes extending in a first direction and being included correspondingly in first and second cell regions that abut relative to a second direction. Each pair including collinear first and second gate segments correspondingly over the first and second ARs, the first and second gate segments being spaced apart in the second direction. The PGBM_1st segment being electrically coupled to the at least one gap-spanning MD contact structure.
Timeline
Filed
06/02/2026
Published
09/24/2026
Granted
Not Available
IPC Codes(5)
H10W 20/41:characterised by their conductive parts
H10D 84/90:Masterslice integrated circuits
H10D 89/10:Integrated device layouts