Abstract
A memory chip includes a memory bank, an I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers is configured to parallelly output a first plurality of data. A width of the I/O data bus is equal to a width of the first plurality of data parallelly outputted by the first plurality of sensing amplifiers.
Full Text
What is claimed is:
A memory chip includes a memory bank, an I/O data bus, and a first plurality of sensing amplifiers. The first plurality of sensing amplifiers is configured to parallelly output a first plurality of data. A width of the I/O data bus is equal to a width of the first plurality of data parallelly outputted by the first plurality of sensing amplifiers.
Timeline
Filed
06/08/2026Published
09/24/2026Granted
Not AvailableIPC Codes(3)
G06F 13/16:for access to memory bus (takes precedence G06F 13/28)
G11C 11/4091:Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4093:Input/output [I/O] data interface arrangements, e.g. data buffers