Abstract
An address counter comprises a flip-flop for performing a load operation of loading a start column address signal, responsive to a first logic signal provided to the flip-flop SET terminal and a second logic signal provided to a RESET terminal and for performing a counting operation of sequentially increasing a data value of the start column address signal.
Full Text
What is claimed is:
An address counter comprises a flip-flop for performing a load operation of loading a start column address signal, responsive to a first logic signal provided to the flip-flop SET terminal and a second logic signal provided to a RESET terminal and for performing a counting operation of sequentially increasing a data value of the start column address signal.
Timeline
Filed
06/05/2026Published
09/24/2026Granted
Not AvailableIPC Codes(2)
G11C 16/08:Address circuits; Decoders; Word-line control circuits
G11C 16/04:using variable threshold transistors, e.g. FAMOS