/Methods Of Manufacturing Semiconductor-on-insulator Wafers Having Charge Trapping Layers With Controlled Stress
Abstract

A method of preparing a multilayer structure includes providing a single crystal semiconductor handle substrate that includes a front surface, a back surface, a circumferential edge joining the front and back surfaces, and a central plane between the front and back surfaces. The single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single crystal semiconductor handle substrate. Depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition after the portion of the semiconductor layer has been deposited to directly anneal the portion of the semiconductor layer after each cycle of the deposition.

Full Text

What is claimed is:

A method of preparing a multilayer structure includes providing a single crystal semiconductor handle substrate that includes a front surface, a back surface, a circumferential edge joining the front and back surfaces, and a central plane between the front and back surfaces. The single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single crystal semiconductor handle substrate. Depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition after the portion of the semiconductor layer has been deposited to directly anneal the portion of the semiconductor layer after each cycle of the deposition.
Timeline
Filed
06/02/2026
Published
09/24/2026
Granted
Not Available
IPC Codes(2)
H10P 90/00:Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
H10W 10/10:Isolation regions comprising dielectric materials