/Semiconductor Structure And Method Of Fabricating Same
Abstract

A method of fabricating a semiconductor device that includes a first die component and at least one second die component. The first die component includes a substrate, a dielectric layer on the substrate, and one or more metal pads positioned on the dielectric layer. The first die component further includes a passivation/bond film layer that is formed over the one or more metal pads, and one or more bond pad vias that extend through the passivation/bond film layer and contact one or more metal pads. The at least one second die component is bonded to the first die component and includes a substrate, and one or more through silicon vias, with the one or more through silicon vias contacting the one or more bond pad vias.

Full Text

What is claimed is:

A method of fabricating a semiconductor device that includes a first die component and at least one second die component. The first die component includes a substrate, a dielectric layer on the substrate, and one or more metal pads positioned on the dielectric layer. The first die component further includes a passivation/bond film layer that is formed over the one or more metal pads, and one or more bond pad vias that extend through the passivation/bond film layer and contact one or more metal pads. The at least one second die component is bonded to the first die component and includes a substrate, and one or more through silicon vias, with the one or more through silicon vias contacting the one or more bond pad vias.
Timeline
Filed
06/15/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(5)
H10W 74/10:characterised by their shape or disposition
H10W 72/20:Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
H10W 72/00:Interconnections or connectors in packages