Abstract
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.
Full Text
What is claimed is:
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.
Timeline
Filed
06/12/2026Published
10/01/2026Granted
Not AvailableIPC Codes(3)
H10W 20/00:Interconnections in chips, wafers or substrates
H10W 20/20:Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/41:characterised by their conductive parts