Abstract
A semiconductor arrangement is provided and includes a first dielectric layer over an optical device. A first metallization layer is over the first dielectric layer, and a first conductive line is in the first metallization layer. A first conductive via is in the first metallization layer and contacts the first conductive line. A second metallization layer is over the first metallization layer. A second conductive line is in the second metallization layer and contacts the first conductive via at a first interface. A heater is over the optical device and has a lowermost surface below the first interface and an uppermost surface above the first interface.
Full Text
What is claimed is:
A semiconductor arrangement is provided and includes a first dielectric layer over an optical device. A first metallization layer is over the first dielectric layer, and a first conductive line is in the first metallization layer. A first conductive via is in the first metallization layer and contacts the first conductive line. A second metallization layer is over the first metallization layer. A second conductive line is in the second metallization layer and contacts the first conductive via at a first interface. A heater is over the optical device and has a lowermost surface below the first interface and an uppermost surface above the first interface.
Timeline
Filed
06/15/2026Published
10/01/2026Granted
Not AvailableIPC Codes(3)
G02B 6/12:of the integrated circuit kind (electric integrated circuits H10B, H10D 84/00, H10F 19/00, H10F 39/00, H10H 29/00, H10K 19/00, H10K 39/00, H10K 59/00, H10N 19/00, H10N 39/00, H10N 59/00, H10N 69/00, H10N 79/00, H10N 89/00)
G02B 6/13:Integrated optical circuits characterised by the manufacturing method
G02B 6/293:with wavelength selective means