Branch target buffer structures are provided. A device can include a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy of branch target buffers including respective branch target buffers that have progressively slower access times. The device can include a first program counter configured to generate a first program counter value associated with a next instruction of an executing application. The device can include a second program counter configured to predict a second program counter value that is associated with a subsequent instruction of the executing application that is after the next instruction. The device can include first branch prediction circuitry configured to populate a branch target buffer of the branch target buffers based on the second program counter value.