/Memory Device Having Backside Power Vias
Abstract

A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.

Full Text

What is claimed is:

A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.
Timeline
Filed
06/16/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(5)
H10W 20/20:Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10B 10/00:Static random access memory [SRAM] devices
H10D 30/43:having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels