Abstract
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and including a first material having a first electronegativity. A bottom electrode diffusion barrier surrounds the bottom electrode. A metal oxide and/or a metal oxy-nitride is disposed between the bottom electrode and a top electrode. A conductive layer includes a second material that is disposed directly between the bottom electrode diffusion barrier and the bottom electrode. The second material has a second electronegativity that is greater than the first electronegativity based on Pauling's scale.
Full Text
What is claimed is:
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and including a first material having a first electronegativity. A bottom electrode diffusion barrier surrounds the bottom electrode. A metal oxide and/or a metal oxy-nitride is disposed between the bottom electrode and a top electrode. A conductive layer includes a second material that is disposed directly between the bottom electrode diffusion barrier and the bottom electrode. The second material has a second electronegativity that is greater than the first electronegativity based on Pauling's scale.
Timeline
Filed
06/12/2026Published
10/01/2026Granted
Not AvailableIPC Codes(3)
H10N 70/00:Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N 79/00)
H10B 63/00:Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
H10N 70/20:Multistable switching devices, e.g. memristors