/Computational Memory Module
Abstract

A computational memory module including quasi-volatile memory circuits being divided into memory partitions and each being associated with a SRAM circuit; and a memory controller circuit to operate the quasi-volatile memory circuits as one or more quasi-volatile memories. The memory controller circuit includes a processor to access the memory partitions of the quasi-volatile memory circuits using the memory access circuit to exchange data in response to executing processing tasks. In another embodiment, an artificial intelligence (AI) computing system includes memory modules, each including one or more quasi-volatile memory circuits interconnected to at least one memory controller; and an arithmetic function block in communication with the memory modules and performing multiply and accumulate functionalities using data stored in the memory modules and to generate an output data of the AI computing system. The memory modules are accessed to perform read, write and erase memory operations.

Full Text

What is claimed is:

A computational memory module including quasi-volatile memory circuits being divided into memory partitions and each being associated with a SRAM circuit; and a memory controller circuit to operate the quasi-volatile memory circuits as one or more quasi-volatile memories. The memory controller circuit includes a processor to access the memory partitions of the quasi-volatile memory circuits using the memory access circuit to exchange data in response to executing processing tasks. In another embodiment, an artificial intelligence (AI) computing system includes memory modules, each including one or more quasi-volatile memory circuits interconnected to at least one memory controller; and an arithmetic function block in communication with the memory modules and performing multiply and accumulate functionalities using data stored in the memory modules and to generate an output data of the AI computing system. The memory modules are accessed to perform read, write and erase memory operations.
Timeline
Filed
06/11/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(1)
G06F 3/06:Digital input from, or digital output to, record carriers