Abstract
A three-dimensional (3D) memory device including lattice layers and dielectric layers on a substrate, memory pillars vertically penetrating the stack, each of the memory pillars including memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first polygon shape in a horizontal plane parallel to the supporting lattice layers, and supporting buttress (SBT) pillars vertically penetrating the stack located at outside ends of the memory pillars.
Full Text
What is claimed is:
A three-dimensional (3D) memory device including lattice layers and dielectric layers on a substrate, memory pillars vertically penetrating the stack, each of the memory pillars including memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first polygon shape in a horizontal plane parallel to the supporting lattice layers, and supporting buttress (SBT) pillars vertically penetrating the stack located at outside ends of the memory pillars.
Timeline
Filed
06/12/2026Published
10/01/2026Granted
Not AvailableIPC Codes(3)
H10W 42/00:Arrangements for protection of devices (arrangements for thermal protection H10W 40/00)
H10B 41/27:the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27:the channels comprising vertical portions, e.g. U-shaped channels