Abstract
The present disclosure provides an embodiment of a method. The method includes patterning a substrate to form trenches; etching the substrate, thereby modifying the trenches with round tips; forming a stack including conductive layers and dielectric layers in the trenches, wherein the conductive layers and the dielectric layers alternate with one another within the stack; forming an insulating compressive film in the trenches, thereby sealing voids in the trenches; and forming conductive plugs connected to the conductive layers, respectively.
Full Text
What is claimed is:
The present disclosure provides an embodiment of a method. The method includes patterning a substrate to form trenches; etching the substrate, thereby modifying the trenches with round tips; forming a stack including conductive layers and dielectric layers in the trenches, wherein the conductive layers and the dielectric layers alternate with one another within the stack; forming an insulating compressive film in the trenches, thereby sealing voids in the trenches; and forming conductive plugs connected to the conductive layers, respectively.
Timeline
Filed
06/16/2026Published
10/01/2026Granted
Not AvailableIPC Codes(9)
H10D 1/00:Resistors, capacitors or inductors
H10D 1/66:Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10P 14/60:of insulating materials