A package structure is provided. The package structure includes a first chip structure, and the first chip structure has a front-side interconnection structure, a device portion, and a back-side interconnection structure. The device portion is between the front-side interconnection structure and the back-side interconnection structure. The package structure also includes a stack of conductive vias formed in the back-side interconnection structure. Each of the conductive vias is thinner than the back-side interconnection structure. The package structure further includes a second chip structure directly bonded to one of the front-side interconnection structure and the back-side interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
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What is claimed is: