/Package Structure With Integrated Chips
Abstract

A package structure is provided. The package structure includes a first chip structure, and the first chip structure has a front-side interconnection structure, a device portion, and a back-side interconnection structure. The device portion is between the front-side interconnection structure and the back-side interconnection structure. The package structure also includes a stack of conductive vias formed in the back-side interconnection structure. Each of the conductive vias is thinner than the back-side interconnection structure. The package structure further includes a second chip structure directly bonded to one of the front-side interconnection structure and the back-side interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

Full Text

What is claimed is:

A package structure is provided. The package structure includes a first chip structure, and the first chip structure has a front-side interconnection structure, a device portion, and a back-side interconnection structure. The device portion is between the front-side interconnection structure and the back-side interconnection structure. The package structure also includes a stack of conductive vias formed in the back-side interconnection structure. Each of the conductive vias is thinner than the back-side interconnection structure. The package structure further includes a second chip structure directly bonded to one of the front-side interconnection structure and the back-side interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
Timeline
Filed
06/17/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(7)
H10W 90/00:Package configurations
H10P 72/70:for supporting or gripping
H10W 20/41:characterised by their conductive parts