Abstract
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming nanostructured channel regions on a fin or sheet base, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions and the fin or sheet base in the gate openings, performing a first doping process on the oxide layers to form doped oxide layers, depositing a first dielectric layer on the doped oxide layers, performing a second doping process on the first dielectric layer to form a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.
Full Text
What is claimed is:
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming nanostructured channel regions on a fin or sheet base, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions and the fin or sheet base in the gate openings, performing a first doping process on the oxide layers to form doped oxide layers, depositing a first dielectric layer on the doped oxide layers, performing a second doping process on the first dielectric layer to form a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.
Timeline
Filed
06/16/2026Published
10/01/2026Granted
Not AvailableIPC Codes(7)
H10D 64/01:Manufacture or treatment
H10D 30/01:Manufacture or treatment
H10D 30/43:having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels