Abstract
Technology related to calibrating synchronization of a data signal to a forwarded clock signal is described. A circuit includes a receiver circuit and a clock-to-data synchronization circuit. The receiver circuit receives a data signal and includes two inverters and two resistors. The clock-to-data synchronization circuit receives the data signal and the clock signal and determines an indication of synchronization between the data and clock signals. The clock-to-data synchronization circuit adjusts, using the indication, a parameter of the receiver circuit to synchronize the data signal and the clock signal.
Full Text
What is claimed is:
Technology related to calibrating synchronization of a data signal to a forwarded clock signal is described. A circuit includes a receiver circuit and a clock-to-data synchronization circuit. The receiver circuit receives a data signal and includes two inverters and two resistors. The clock-to-data synchronization circuit receives the data signal and the clock signal and determines an indication of synchronization between the data and clock signals. The clock-to-data synchronization circuit adjusts, using the indication, a parameter of the receiver circuit to synchronize the data signal and the clock signal.
Timeline
Filed
06/11/2026Published
10/01/2026Granted
Not AvailableIPC Codes(4)
G06F 1/12:Synchronisation of different clock signals
G06F 1/10:Distribution of clock signals
G06F 13/16:for access to memory bus (takes precedence G06F 13/28)