/Hree-dimensional Integrated Circuit With Hybrid Bond Metal Structure
Abstract

One aspect of the present disclosure pertains to an IC packaging structure that includes a bottom circuit structure having first semiconductor devices on a first substrate, a first interconnect structure over the first semiconductor devices, and a first bonding structure over the first interconnect structure; and a top circuit structure having second semiconductor devices on a second substrate, a second interconnect structure underlying the second semiconductor devices, and a second bonding structure underlying the second interconnect structure. The first bonding structure includes a first metal feature having a first crystalline bulk layer of a metal and a first amorphous surface layer of the metal. The second bonding structure includes a second metal feature having a second crystalline bulk layer of the metal and a second amorphous surface layer of the metal. The top circuit structure is bonded to the bottom circuit structure through the first and second amorphous surface layers.

Full Text

What is claimed is:

One aspect of the present disclosure pertains to an IC packaging structure that includes a bottom circuit structure having first semiconductor devices on a first substrate, a first interconnect structure over the first semiconductor devices, and a first bonding structure over the first interconnect structure; and a top circuit structure having second semiconductor devices on a second substrate, a second interconnect structure underlying the second semiconductor devices, and a second bonding structure underlying the second interconnect structure. The first bonding structure includes a first metal feature having a first crystalline bulk layer of a metal and a first amorphous surface layer of the metal. The second bonding structure includes a second metal feature having a second crystalline bulk layer of the metal and a second amorphous surface layer of the metal. The top circuit structure is bonded to the bottom circuit structure through the first and second amorphous surface layers.
Timeline
Filed
06/15/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(4)
H10W 20/42:Vias, e.g. via plugs
H10W 72/90:Bond pads, in general
H10W 80/00:Direct bonding of chips, wafers or substrates