Abstract
The present disclosure provides a method according to some embodiments. The method includes receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features; modifying the IC layout such that the modified RDL structure meets a criterion associated with a X-Y ratio gap; generating a tape-out according to the modified IC layout; and fabricating the semiconductor structure according to the modified IC layout defined in the tape-out.
Full Text
What is claimed is:
The present disclosure provides a method according to some embodiments. The method includes receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features; modifying the IC layout such that the modified RDL structure meets a criterion associated with a X-Y ratio gap; generating a tape-out according to the modified IC layout; and fabricating the semiconductor structure according to the modified IC layout defined in the tape-out.
Timeline
Filed
06/15/2026Published
10/01/2026Granted
Not AvailableIPC Codes(9)
H10P 72/00:Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
H10P 74/20:characterised by the properties tested or measured, e.g. structural or electrical properties
H10P 76/20:of masks comprising organic materials