Abstract
A method for manufacturing a semiconductor structure is provided. The method includes forming a transistor over the first wafer; bonding a first wafer to a second wafer; trimming an edge region of the first wafer along a circular trimming path, wherein a center of the circular trimming path is offset from a center of the second wafer in a top view; after trimming the edge region of the first wafer, thinning down the first wafer; and after thinning down the first wafer, forming a backside conductive feature electrically connected to the transistor.
Full Text
What is claimed is:
A method for manufacturing a semiconductor structure is provided. The method includes forming a transistor over the first wafer; bonding a first wafer to a second wafer; trimming an edge region of the first wafer along a circular trimming path, wherein a center of the circular trimming path is offset from a center of the second wafer in a top view; after trimming the edge region of the first wafer, thinning down the first wafer; and after thinning down the first wafer, forming a backside conductive feature electrically connected to the transistor.
Timeline
Filed
06/17/2026Published
10/01/2026Granted
Not AvailableIPC Codes(2)
H10P 52/00:Grinding, lapping or polishing of wafers, substrates or parts of devices
H10W 20/00:Interconnections in chips, wafers or substrates