/Field Effect Transistor With Gate Isolation Structure And Method
Abstract

A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.

Full Text

What is claimed is:

A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.
Timeline
Filed
06/16/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(5)
H10D 30/43:having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 30/01:Manufacture or treatment
H10D 30/67:Thin-film transistors [TFT]