/Semiconductor Structure And Manufacturing Method Thereof
Abstract

A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.

Full Text

What is claimed is:

A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.
Timeline
Filed
06/11/2026
Published
10/01/2026
Granted
Not Available
IPC Codes(13)
H10W 70/60:Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W 70/40)
H10W 70/09:extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
H10W 70/63:Vias, e.g. via plugs